Design and Implementation of Low Latency CORDIC Algorithm in Field Programmable Gate Array
نویسندگان
چکیده
Coordinate Rotation Digital Computer is a general purpose digital computer for the real time computations. At present the need of Multipliers is increasing in various real time domains which have the core operations like trigonometric computations, Multiplication and Division. The three important parameters which affect the current trends of VLSI domains are power, speed and area. Usage of conventional multipliers in the design will result in more power and area consumption. CORDIC algorithm is an effective replacement of the Multipliers by using adders/ subtractor and shifters. The objective of this work is to design and implement a low power Iterative and high performance Pipelined architecture for trigonometric computations using CORDIC algorithm. The two different VLSI architectures were designed and functionally verified using Modelsim 10.1b Simulator. The designs were implemented in Field Programmable Gate Array (FPGA) using Altera Quatrus II Synthesis tools.
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